Wafer-Level Chip-Scale Packaging

Wafer-Level Chip-Scale Packaging

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Analog and Power Wafer Level Chip Scale Packaging presents a state-of-art and in-depth overview in analog and power WLCSP design, material characterization, reliability and modeling. Recent advances in analog and power electronic WLCSP packaging are presented based on the development of analog technology and power device integration. The book covers in detail how advances in semiconductor content, analog and power advanced WLCSP design, assembly, materials and reliability have co-enabled significant advances in fan-in and fan-out with redistributed layer (RDL) of analog and power device capability during recent years. Since the analog and power electronic wafer level packaging is different from regular digital and memory IC package, this book will systematically introduce the typical analog and power electronic wafer level packaging design, assembly process, materials, reliability and failure analysis, and material selection. Along with new analog and power WLCSP development, the role of modeling is a key to assure successful package design. An overview of the analog and power WLCSP modeling and typical thermal, electrical and stress modeling methodologies is also presented in the book.1.3 Fan-In Versus Fan-Out With every new product generation, portable electronic devices such as smart phones or ... In both fan-in and fan-out cases, no laminate substrate or epoxy mold compound is needed to connect the die to the PWBanbsp;...

Title:Wafer-Level Chip-Scale Packaging
Author:Shichun Qu, Yong Liu
Publisher:Springer - 2014-09-10


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