The escalating impact of environmental and process variations on the performance of current and future technology VLSI circuits, necessitates the use of circuit design techniques that can account for these uncertainties.mum wire pitches (pmin), were taken from [SIA01] and [ConOO] for power delivery to a 2cm x 2cm chip in 130nm technology with Vdd = 1-2V. The voltage constraints for the power grids, i.e., Vspec was 1.08V, i.e., 90% of Vdd- The via specificanbsp;...
|Title||:||Variation-aware Computer-aided Design Techniques for VLSI Digital Circuits|
|Author||:||Jaskirat Singh Bindra|
|Publisher||:||ProQuest - 2006|