Tutorial test generation for VLSI chips

Tutorial test generation for VLSI chips

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For simple devices, manual generation offers low cost in terms of equipment and time. Automatic test generation ... A test partem is a truth table that has two dimensions: one for device pins (41 In this example) and one for time flow (1 6 i In this example) during the test. Fig 1. Depending on ... In real-world test environments, test engineers often reduce their tests to meaningful subsets of aquot; testing everything.

Title:Tutorial test generation for VLSI chips
Author:Vishwani D. Agrawal, Sharad C. Seth, IEEE Computer Society
Publisher:IEEE Computer Society - 1988


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