Timing and Power Analysis of CMOS Logic Cells Under Noisy Inputs

Timing and Power Analysis of CMOS Logic Cells Under Noisy Inputs

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This dissertation investigates the effect of capacitive crosstalk on the behavior of CMOS cells and presents a new cell modeling technique for the purpose of noise, delay and power analysis. In particular, a current-based logic cell model for cell timing analysis in the presence of crosstalk-induced noisy inputs is introduced. This model enables accurate calculation of the electrical waveform of the cell output under noise-affected input waveforms of arbitrary shapes. This current source (CS) model is subsequently extended to handle multiple input switching (MIS) while considering the effect of internal node voltages of the transistor stacks in the cell (a.k.a. the stack effect). Application of the proposed CS model for short-circuit power analysis is presented. In addition, a CS model for CMOS register cells i.e., latches and master-slave flip-flops is described. Experimental results for the proposed CS models demonstrate close-to-SPICE accuracy with up to 3 orders of magnitude speedup compared to HSpice. The scope of this dissertation is not limited to delay and power analyses. Indeed, this dissertation also investigates the problem of power-optimal repeater insertion for global buses in the presence of crosstalk noise and subject to delay constraints.A well-known equation for time- 3 1 averaged short-circuit power dissipation is [ 63]: (2)12scinddTPkVV f I„ Ip =aˆ’ where inI„ is the input transition time, TV is the threshold voltage of transistors, and k is the effective transconductance parameter ofanbsp;...

Title:Timing and Power Analysis of CMOS Logic Cells Under Noisy Inputs
Author:Hanif Fatemi
Publisher:ProQuest - 2007


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