This is the definitive reference for the latest generation of the enormously popular and influential SPARC microprocessors a the 64-bit SPARC-V9 a which is now being used by a variety of computer system vendors and is destined to set the standard for high performance capacity into the next century. Describes the architecture and instruction set of the 64-bit SPARC-V9 a a RISC-style processor architecture that supports a linear address space accessed by 64-bit addresses, fault-tolerance, object-oriented software, lightweight threads, and superscalar and multiprocessor implementations. MARKETS: For implementors of the SPARC architecture, microprocessor designers, hardware engineers, developers of SPARC-V9 system software, software engineers who write SPARC-V9 software in assembly language; and for students of computer architecture.... 42, 212, 242 floating-point state (FSR), 43, 48, 50, 171, 222, 243, 246, 250 frame pointer, 292 global, 4, 15, 30, 30, 30, ... instructions, 131 instructions, 82 opcodes, 311 reset externally initiated (XIR), 89, 91, 95, 109 extemallyJnitiated( XlR), anbsp;...
|Title||:||The SPARC Architecture Manual|
|Author||:||David L. Weaver, Tom Germond|
|Publisher||:||Prentice Hall - 1994|