This is the first book to cover verification strategies and methodologies for SOC verification from system level verification to the design sign-off. All the verification aspects in this exciting new book are illustrated with a single reference design for Bluetooth application.Excerpts from Timing Analysis Run cmdagt; include arbiter.cmd arbiter.cmdagt; logfile arbiter.log arbiter.cmdagt; readtechnology ./std-cell.tech ... The readverilog command reads in the Verilog code. toplevelcell sets the top-level to asb_arbiter.
|Author||:||Prakash Rashinkar, Peter Paterson, Leena Singh|
|Publisher||:||Springer Science & Business Media - 2007-05-08|