In synchronous digital ICs, switching noise affects the timing characteristics of a circuit by generating additional delay uncertainty, possibly degrading system performance or causing a circuit to fail. Interdependent setup and hold times are characterized and exploited to compensate for delay uncertainty, producing a more robust circuit tolerant to switching noise. The proposed algorithms are demonstrated on industrial circuits, verifying the efficiency of exploiting interdependence in reducing delay uncertainty. The research presented in this dissertation provides methodologies and algorithms for designing both mixed-signal and synchronous digital ICs with superior noise performance and enhanced signal integrity.Chapter 9 Exploiting Setup-Hold Time Interdependence in Timing Analysis The effects of switching noise in mixed signal circuits have been studied in Chapters 4, 5, 6, 7, and 8 with a primary focus on worst-case power/ground noiseanbsp;...
|Title||:||Switching Noise and Timing and Characteristics in Nanoscale Integrated Circuits|
|Publisher||:||ProQuest - 2009|