The size of technically producible integrated circuits increases continuously, but the ability to design and verify these circuits does not keep up. Therefore todayas design flow has to be improved. Using a visionary approach, this book analyzes the current design methodology and verification methodology, a number of deficiencies are identified and solutions suggested. Improvements in the methodology as well as in the underlying algorithms are proposed.Then, automatic property generation was used in the manner explained in Section 5.2.3. Due to the new methodology, two errors were detected. The Verilog code of the arbiter is shown in Figure 5.12 on page 96. Originally, instead of Lines 16anbsp;...
|Title||:||Robustness and Usability in Modern Design Flows|
|Author||:||Görschwin Fey, Rolf Drechsler|
|Publisher||:||Springer Science & Business Media - 2008-01-08|