E. Sequential modified Booth multiplier This is a sequential multiplier that calculates the result in several clock cycles by ... The result is a VHDL synthesizable code, according to the Synopsys Design Compiler synthesis rules, although it cananbsp;...
|Title||:||Proceedings of the IECON '97|
|Author||:||IEEE Industrial Electronics Society, Keisoku Jidō Seigyo Gakkai (Japan)|
|Publisher||:||Institute of Electrical & Electronics Engineers(IEEE) - 1997|