Interface synthesis has been considered as an integral part of all the codesign envirnments with varying degree of emphasis ... Issues which are not handled automatically here are: determination of queue length, communication address mechanism, and arbitration mechanism. ... for synthesis of Verilog code in the form of a finite state machine which ensures consistent data transfers between two IPanbsp;...
|Title||:||Proceedings, ... International Symposium on VLSI Design|
|Author||:||IEEE Circuits and Systems Society|
|Publisher||:||IEEE - 2000|