We strongly favor the use of dataflow instructions to reduce the complexity of the processor by eliminating complex logic needed for resolving data dependencies, branch prediction, register renaming and instruction scheduling on superscalar implementations. Although the results presented here are based on synthetic benchmarks and Monte Carlo simulations, the ...  R. Govindarajan, S.S. Namawarkar and P. LeNir, aquot;Design and performance evaluation of a multithreadedanbsp;...
|Title||:||Parallel Architectures, Agorithms, and Networks|
|Author||:||Albert Y. Zomaya|
|Publisher||:||Institute of Electrical & Electronics Engineers(IEEE) - 1999|