This book offers readers a set of new approaches and tools a set of tools and techniques for facing challenges in parallelization with design of embedded systems. It provides an advanced parallel simulation infrastructure for efficient and effective system-level model validation and development so as to build better products in less time. Since parallel discrete event simulation (PDES) has the potential to exploit the underlying parallel computational capability in todayas multi-core simulation hosts, the author begins by reviewing the parallelization of discrete event simulation, identifying problems and solutions. She then describes out-of-order parallel discrete event simulation (OoO PDES), a novel approach for efficient validation of system-level designs by aggressively exploiting the parallel capabilities of todaysa multi-core PCs. This approach enables readers to design simulators that can fully exploit the parallel processing capability of the multi-core system to achieve fast speed simulation, without loss of simulation and timing accuracy. Based on this parallel simulation infrastructure, the author further describes automatic approaches that help the designer quickly to narrow down the debugging targets in faulty ESL models with parallelism.References. [AG96] Ken Arnold and James Gosling. The Java Programming Language. Addison-Wesley, 1996. [Ana] Analog Devices, Inc., The Blackfin Processor. http://www.analog.com/en/processorsdsp/blackfin/products/index.html . [Are] Areoflex Gaisler ... [art09a] IEEE Standard for SystemVerilog-Unified Hardware Design, Specification, and Verification Language. IEEE Standard 1800 a2009, 2009. [art09b] IEEE Standard VHDL Language Reference Manual. IEEE Standardanbsp;...
|Title||:||Out-of-order Parallel Discrete Event Simulation for Electronic System-level Design|
|Publisher||:||Springer - 2014-07-24|