Utilization of a macrocell design approach and a 1/i rule Si bipolar super self- aligned process technology (SST)1 make it possible to achieve 8fJps/gate and 2.6mW/gate for an LCML basic circuit on the macrocell array chip. Using this macrocell ... The basic layout pattern consists of 2 internal cells as shown in Figure 2. Each cell ... The 26 second metal channels are allocated for power and reference buses. Moreover, 16 ... The carry- save adder (CSA) array algorithm is employed.
|Title||:||IEEE 1985 International Solid-State Circuits Conference|
|Author||:||Lewis Winner, J. A. A Raper|