Reported in this study are three different gate designs which help to optimize the electric field in the channel of a transistor. Donald A. Neamen, Semiconductor and Physics and devices Third Edition, TATA McGraw Hill. ... of device performance in vertical sub- 100 nm MOS devices due to local channel dopingaquot;, Solid-State Electronics 46, 387-391, (2002). ... Solid-State and Integrated Circuit Technology, 860 - 862 (2006)  Sasaki, Y., Nagahama, K., Hosono, K., Katoh, T., Komaru, ...  Till Kuendiger, G. Michael Howard, Pedram Mokrian, Majid Ahmadi, W.C. Miller, Design and Analysis of Planar andanbsp;...
|Title||:||Gate Designs to Optimize Electric Field in FETs|
|Publisher||:||ProQuest - 2008|