To demonstrate the idea, a prototype has been designed and fabricated in 0.13microm with 1.35V power supply. The system mainly consists of a pipelined ADC, a reference ADC, and an adaptive digital filter in FPGA. The measured results show that the SNR improves from 28.1dB before calibration to 59.4dB after calibration at 10OMS/s with a 411kHz. The SFDR improves from 29.8dB to 67.8dB. The total power consumption of the chip is 448mW and the estimated power consumption of the adaptive digital filter is 7mW at 100MHz.The pipelined ADC, the reference ADC, and the LMS adaptive filter are modeled using SimulinkAr blocks . To reduce the ... the first stage of. 22 Behavioral Simulations Error correction of pipelined ADC: code-domain LMS adaptive equalizer.
|Title||:||Digitally Calibrated Analog-to-digital Converters in Deep Sub-micron CMOS.|
|Author||:||Cheongyuen William Tsang|
|Publisher||:||ProQuest - 2008|