Digital VLSI Design with Verilog

Digital VLSI Design with Verilog

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This unique textbook is structured as a step-by-step course of study along the lines of a VLSI IC design project. In a nominal schedule of 12 weeks, two days and about 10 hours per week, the entire verilog language is presented, from the basics to everything necessary for synthesis of an entire 70, 000 transistor, full-duplex serializer - deserializer, including synthesizable PLLs. Digital VLSI Design With Verilog is all an engineer needs for in-depth understanding of the verilog language: Syntax, synthesis semantics, simulation, and test. Complete solutions for the 27 labs are provided on the accompanying CD-ROM. For a reader with access to appropriate electronic design tools, all solutions can be developed, simulated, and synthesized as described in the book. A partial list of design topics includes design partitioning, hierarchy decomposition, safe coding styles, back-annotation, wrapper modules, concurrency, race conditions, assertion-based verification, clock synchronization, and design for test. Coverage of specific devices includes basic discussion and exercises on flip-flops, latches, combinational logic, muxes, counters, shift-registers, decoders, state machines, memories (including parity and ECC), FIFOs, and PLLs. Verilog specify blocks, with their path delays and timing checks, also are covered.Based onan HDLCon 2000 presentation. http://www.sutherland- papers/ 2000-HDLCon-paperVerilog-2000.pdf. Fig. 23.1 Sketch of PLI relationship to simulation and synthesis flows. 418 23 Week 12 Class 1 23.2 Continued Lab Workanbsp;...

Title:Digital VLSI Design with Verilog
Author:John Williams
Publisher:Springer Science & Business Media - 2008-06-06


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