Being able to test and screen chips is a key factor in achieving high yield. Most industry standard CAD tools used to analyze fault coverage and generate test vectors require gate level models. However, since caches are typically designed using a transistor-level flow, there is a need for an abstraction step to generate the gate models, which must be equivalent to the actual design (transistor level). The third contribution of the research is a framework to verify that the gate level representation of custom designs is equivalent to the transistor-level design.49 Figure 4-15: Traditional and RVS high circuit and waveform for SRAM wordline..................... 50 Figure 4-16 SRAM-based memory main block showing the RVS control circuit location.......... 51 Figure 5-1: Block diagram of the test chip.
|Title||:||Cache Design for Low Power and Yield Enhancement|
|Author||:||Baker Shehadah Mohammad|
|Publisher||:||ProQuest - 2008|