A widely read and authoritative book for hardware and software designers. This innovative book exposes the characteristics of performance-optimal single- and multi-level cache hierarchies by approaching the cache design process through the novel perspective of minimizing execution time.... 278 precharge and equalize, 279a80 read and write multiplexers, 280 read and write timing diagram, 278 permanent store, ... 508a9 phase-change RAM ( PCRAM), 5 phase-Locked Loop (PLL), 335, 400, 401a2 block diagram, 401 on- chip, anbsp;...
|Title||:||Cache and Memory Hierarchy Design|
|Author||:||Steven A. Przybylski|
|Publisher||:||Morgan Kaufmann - 1990|