Boundary-Scan Test

Boundary-Scan Test

4.11 - 1251 ratings - Source

The ever-increasing miniaturization of digital electronic components is hampering the conventional testing of Printed Circuit Boards (PCBs) by means of bed-of-nails fixtures. Basically this is caused by the very high scale of integration of ICs, through which packages with hundreds of pins at very small pitches of down to a fraction of a millimetre, have become available. As a consequence the trace distances between the copper tracks on a printed circuit board cmne down to the same value. Not only the required small physical dimensions of the test nails have made conventional testing unfeasible, but also the complexity to provide test signals for the many hundreds of test nails has grown out of limits. Therefore a new board test methodology had to be invented. Following the evolution in the IC test technology. Boundary-Scan testing hm; become the new approach to PCB testing. By taking precautions in the design of the IC (design for testability), testing on PCB level can be simplified 10 a great extent. This condition has been essential for the success of the introduction of Boundary-Sc, m Test (BST) at board level.The MCERT chip is designed to execute user defined memory test algorithms. Four march test registers in the ... Tests may be stopped on the occurrence of the first memory error and restarted from the last failing location. a€c A failing location is anbsp;...

Title:Boundary-Scan Test
Author:Harry Bleeker, Peter van den Eijnden, Frans de Jong
Publisher:Springer Science & Business Media - 2011-06-28


You Must CONTINUE and create a free account to access unlimited downloads & streaming