Due to the exponential increase of subthreshold and gate leakage currents with technology scaling, leakage power is increasingly significant in CMOS circuits as the technology scales down. The leakage power is as much as 50% of the total power in the 90nm technology and is becoming dominant in more advanced CMOS technologies with smaller feature sizes. Also, the leakage in active mode is significantly larger due to the higher die temperature in active mode. Although many leakage reduction techniques have been proposed, most of them can only reduce the circuit leakage power in standby mode.If we turn on the power of each gate within its switching window like this in each clock cycle, we cannot save much leakage power. 188.8.131.52 Minimal Switching Window To solve the problem of the switching window, we propose another type of timing window, named the minimal switching ... The load capacitance C is calculated using the parameters and equations defined in the BSIM3v3 model manual.
|Title||:||A Novel Dynamic Power Cutoff Technology (DPCT) for Active Leakage Reduction in Deep Submicron VLSI CMOS Circuits|
|Publisher||:||ProQuest - 2007|