The block diagram in FIG. 4-4 shows how bus control logic provides the control signals for data buffers. the memory latches. and memory devices. It also returns RDY# active to end the 80486 bus cycle and NA# to control address pipelining.
|Author||:||Penn Brumm, Don Brumm, Leo J. Scanlon|
|Publisher||:||Tab Books - 1991|